1. Field of the Invention
The present invention relates to a memory, and more particularly, it relates to a memory including memory cells holding data.
2. Description of the Background Art
A ferroelectric memory including memory cells holding data is known in general, as disclosed in Japanese Patent Laying-Open No. 2002-133857, for example.
In the ferroelectric memory including memory cells disclosed in the aforementioned Japanese Patent Laying-Open No. 2002-133857, a charge transfer transistor is connected to each bit line connected with the corresponding memory cell and a capacitor storing charge for controlling transfer of the charge from the bit line to the capacitor. In data reading, the ferroelectric memory determines data read from the memory cell on the basis of a voltage resulting from the charge transferred from the memory cell to the capacitor through the bit line and the charge transfer transistor. Further, the ferroelectric memory disclosed in Japanese Patent Laying-Open No. 2002-133857 generates a voltage corresponding to the threshold voltage Vt of the charge transfer transistor through the threshold voltage of a p-channel transistor in a separately provided threshold voltage generation circuit before reading the data. The ferroelectric memory applies the generated threshold voltage to the gate of the charge transfer transistor for holding the gate-to-source voltage VGS of the charge transfer transistor at the threshold voltage Vt, thereby holding the charge transfer transistor in an OFF-state in the vicinity of a boundary state between ON- and OFF-states. Thus, the ferroelectric memory disclosed in the aforementioned Japanese Patent Laying-Open No. 2002-133857 inputs the charge responsive to the data of the memory cell in the source of the charge transfer transistor from the bit line in data reading, for turning on the charge transfer transistor in response to the gate-to-source voltage VGS falling below the threshold voltage Vt. The ferroelectric memory transfers the charge corresponding to the data of the memory cell to the capacitor from the bit line through the charge transfer transistor in this manner.
However, the ferroelectric memory disclosed in the aforementioned Japanese Patent Laying-Open No. 2002-133857 generates the voltage corresponding to the threshold voltage Vt applied to the gate of the charge transfer transistor through the threshold voltage of the p-channel transistor in the separately provided threshold voltage generation circuit when holding the charge transfer transistor in the OFF-state in the vicinity of the boundary state between ON- and OFF-states before reading the data. If the threshold voltage of the p-channel transistor in the threshold voltage generation circuit is dispersed due to dispersion in a manufacturing process, therefore, the threshold voltage generation circuit may disadvantageously generate a voltage different from the threshold voltage Vt of the charge transfer transistor. In this case, the gate-to-source voltage VGS of the charge transfer transistor resulting from the voltage received in the gate from the threshold voltage generation circuit is smaller or larger than the threshold voltage Vt, and hence the charge transfer transistor disadvantageously shifts to a state closer to an OFF-state or enters an ON-state from the OFF-state in the vicinity of the boundary state between ON- and OFF-states before the ferroelectric memory reads the data. If the charge transfer transistor shifts to the state closer to an OFF-state, therefore, the ferroelectric memory can only partially transfer the charge responsive to the data of the memory cell since the charge transfer transistor does not enter an ON-state until the potential of the bit line rises to a prescribed level despite the charge output from the memory cell to the bit line. If the charge transfer transistor enters an ON-state, on the other hand, a negative potential supplied from the capacitor to the bit line through the ON-state charge transfer transistor before the ferroelectric memory reads the data disadvantageously causes partial disappearance of the charge of the memory cell thereafter output to the bit line. Consequently, it is so difficult to sufficiently transfer the charge corresponding to the data held in the memory cell to the capacitor that a reading voltage is disadvantageously reduced in data reading.